The invention relates to a semiconductor memory device, and more particularly to an improvement in high density stacked capacitor cells for a dynamic random access memory (DRAM).
The importance of high integration of a stacked capacitor cell array for the dynamic random access memory has been on the increase in the semiconductor technology. An improvement in the high integration of the stacked capacitor cell array in the dynamic random access memory device requires each memory cell to occupy a small area as much as possible. The each memory cell includes a stacked capacitor serving as a storage capacitor and a field effect transistor serving as a switching transistor. Concurrently, a security of a predetermined capacitance is essential to support an excellent performance of the each stacked capacitor as a storage capacitor in the each memory cell. Scaling down of the each stacked capacitor and thus high density of the stacked capacitor cell array is essential to allow the memory cell array device or the dynamic random access memory device to exhibit excellent and high level performances as the memory device. The security of a predetermined capacitance or a relatively large capacitance for the each stacked capacitor is also essential to provide both a high reliability and a excellent performance to the stacked capacitor memory cell array device or the dynamic random access memory device. Many structures about the stacked capacitor have been proposed for improvements both in the high integration of the stacked capacitor cell array and in the enlargement of the capacitance of each the stacked capacitor in the dynamic random access memory device.
A typical structure of each stacked capacitor memory cell in a conventional dynamic random access memory device will be described with reference to FIG. 1. The structure of the each stacked capacitor cell in the dynamic random access memory device has a p-type silicon substrate 301. Field oxide films 302 are selectively formed in a surface area of the p-type silicon substrate 301 thereby an active region for formation of the stacked capacitor cell is defined in the surface area of the p-type silicon substrate 301. Both a gate oxide film 303 and a gate electrode 304 which exists on the gate oxide film 303 are formed in a predetermined area in the active region of the p-type silicon substrate 301. Further, n-type diffusion regions 305-1 and 305-2 to serve as source and drain regions are formed in the active region except for an area directly under the gate oxide film 303 and the gate electrode 304 thereby a channel region directly under both the gate oxide film 303 and the gate electrode 304 is defined by the n-type source and drain diffusion regions 305-1 and 305-2. A first inter-layer insulator 306 is so formed as to overlay an entire surface of the device, for example, the field oxide film 302, the n-type source and drain diffusion regions 305-1 and 305-2 and the gate electrode 304. The first inter-layer insulator 306, however, has a through hole directly over the source or drain diffusion region 305-1. A storage capacitor 308 for a stacked capacitor cell is so formed as to contact to the n-type source or diffusion region 305-1 through the contact hole of the first inter-layer insulator 306. The storage electrode 308 of the stacked capacitor cell has a vertical side wall above the first inter-layer insulator 306 such as to have a relatively large height as compared to its size. A capacitive insulation film 309 for the stacked capacitor is so formed as to cover an exposed surface of the storage electrode 308 above the first inter-layer insulator 306. Further, an opposite electrode 310 for the stacked capacitor is so formed as to overlay the capacitive insulation film 309 thereby resulting in a formation of the stacked capacitor in the memory cell. The capacitance of the stacked capacitor is formed by a combination of the storage and opposite electrodes 308 and 310 through the capacitive oxide film 309. A second inter-layer insulator 307 is so formed as to overlie an entire surface of the device, for example, the first inter-layer insulator 306 and the opposite electrode 310 of the stacked capacitor.
Actually, a plurality of word-lines and bit-lines are formed over the second inter-layer insulator 307, although illustrations thereof are omitted from FIG. 1. The plural word-lines and bit-lines are, of course, electrically separated from each other. The word-lines are crossed to the bit-lines with an overpass. The bit-lines comprise wiring layers made of polycide. The word-lines also comprise wiring layers but made of aluminium which provide a low resistance to the word-lines. The n-type source or drain diffusion region 305-2 is connected to the bit-line, although an illustration of this connection between the bit-line and the n-type source or drain diffusion region 305-2 is omitted from FIG. 1.
Digital signals are transmitted through any one of the plural bit-lines to the n-type source or drain diffusion region 305-2 of the transistor. When the transistor takes ON state, the digital signal is transmitted though the channel region to the n-type source or drain diffusion region 305-1, and subsequently transmitted into the storage electrode 308 of the stacked capacitor. The transistor turns OFF thereby the digital signal is stored in the storage electrode 308 of the stacked capacitor.
With respect to the capacitance of the stacked capacitor, a value of the capacitance of the stacked capacitor depends upon a size of a surface area of the capacitive oxide film 309 which is sandwiched between the storage and opposite electrodes 308 and 310. A security of a large area of interfaces of the capacitive oxide film 309 to the storage and opposite electrodes 308 and 310 provides a large capacitance to the stacked capacitor. A small occupied area of the stacked capacitor allows the accomplishment of the high integration of the stacked memory cell array. The storage electrode 308 of the stacked capacitor having the side portion abutting the capacitive oxide film 309 of the stacked capacitor is so designed that the side portion of the storage electrode 308 has such a large height as to secure a large area of the interface of the storage electrode 308 to the capacitive oxide film 309 under the condition of a small occupied area of the stacked capacitor. Such security of the large area of the interfaces of the capacitive oxide film 309 to the storage and opposite electrodes 308 and 310 for the stacked capacitor under the condition of the small occupied area of the stacked capacitor not only permits the accomplishment of the high integration of the memory cell array but also provides a required capacitance relatively large as compared to the stacked capacitor.
Such structure of the stacked capacitor cell for the dynamic random access memory device is, however, engaged with the following disadvantages. As illustrated in FIG. 1, a surface of the second inter-layer insulator 307 exhibits a large difference in level at a boundary area between a memory cell area and a peripheral area. Namely, the surface of the second inter-layer insulator 307 over the stacked capacitor exists above the surface of the second inter-layer insulator 307 over the field oxide film 302. As described the above, the bit-lines and the word-lines are formed over the second inter-layer insulator 307. That is why the bit-lines and the word-lines also have such a difference in level as the large difference in level of the second inter-layer insulator 307. Such large difference in level of the second inter-layer insulator 307 is caused from the large height of the vertical side wall of the stacked capacitor above the inter-layer insulator 306. Although such structure of the stacked capacitor having the vertical side wall with the large height allows the above requirements concerned with the small occupied area and the large capacitance of the stacked capacitor to be satisfied, the large height of the vertical side wall of the stacked capacitor above the first inter-layer insulator 306 provides the large differences in level not only to the second inter-layer insulator 307 but also to the word-lines and the bit-lines above the first inter-layer insulator 306. The large difference in level of the wiring layers of the bit-lines or the word-lines causes the following problems in both the high integration and the high reliability of the dynamic random access memory device.
One of the most important factors for accomplishment of the scaling down of the each memory cell, which allows the high integration of the memory cell array in the dynamic random access memory device, is the accuracy of patterning provided by a photo-lithography process. Namely, how much scaling down of the dynamic random access memory is achievable depends upon a grade of the accuracy of the patterning provided by the present photo-lithography technique. The grade of the accuracy of the patterning provided by the photo-lithography depends upon a degree of leveling of a surface of a layer which is exposed to ultraviolet rays for the patterning by the photo-lithography. A high grade leveling of a surface of a layer to be exposed to the patterning by the photo-lithography allows an accomplishment of a high accuracy of the patterning by the photo-lithography. In contrast, a low grade leveling of a surface of a layer to be exposed to the patterning by the photo-lithography does not allow any accomplishment of a high accuracy of the patterning by the photo-lithography. Namely, a large difference in level of a surface of a layer to be exposed to the patterning by the photo-lithography makes the accuracy of the patterning by the photo-lithography inferior. A fine pattern or a high grade accuracy of the patterning by the photo-lithography is essential for improvement in the scaling down of the device. Inferiority of the accuracy of the patterning by the photo-lithography makes it difficult to improve the scaling down of the device. Existence of a large difference in level of a surface of a layer in the device, thus, provides the inferiority to the accuracy of the patterning by the photo-lithography and thus resulting in a difficulty in the scaling down of the device, although the scaling down is necessary for improvement in the high integration of the device. Elimination of the difference in level and thus implementation of a high grade leveling of a surface of each layer in the device is essential for improvement in the scaling down which allows a high integration of the device.
Indeed, as understood from FIG. 1, the conventional dynamic random access memory cell device has a remarkable difference in level of the second inter-layer insulator 307 at the boundary area between the memory cell area and the peripheral area. That is why the bit-lines and the word-lines which are formed over the second inter-layer insulator 307 also have such a remarkable difference in level which causes the inferiority in the accuracy of the patterning by the photo-lithography. The inferiority in the accuracy of the patterning by the photo-lithography for the bit-lines and the word-lines provides a restriction to the improvement in the scaling down of the dynamic random access memory device thereby resulting in an inferior yield of the device.
Accomplishment of an excellent leveling for a surface of each layer, particularly the second inter-layer insulator 307, wiring-layers such as bit-lines and word-liners is, therefore, essential to improve a high integration of the memory cell device such as stacked capacitor cell random access memory device.
It is, thus, required to develop a novel stacked capacitor memory cell device for memory cell array of a random access memory device, which allows a leveled surface of each layer, particularly the second inter-layer insulator 307, wiring-layers such as bit-lines and word-liners.